Method of fabricating a dram cell with a plurality of vertical extensions

ABSTRACT

Fabricating a DRAM memory cell with increased capacitance by increasing the surface area of a storage electrode of a storage capacitor includes forming transfer transistor having a gate electrode and source-drain electrode areas on a semiconductor substrate. First, second and third insulating layers are formed in sequence on the semiconductor substrate and the transfer transistor. The third, second and first insulating layers are selectively etched through to form a contact opening exposing one of the source-drain electrode areas as a contact area. An upper portion of the third insulating layer is etched to form a plurality of first trenches. A first conductive layer is formed over the insulating layer filling the contact opening and the first trenches. An upper portion of the first conductive layer is etched to form a plurality of second trenches, and selectively etched to define a pattern area of a storage electrode of a capacitor. The storage electrode includes a vertical frame which contacts the contact area through the contact opening, and a horizontal plate having a plurality of extending areas which extend out vertically therefrom. Using the second insulating layer as an etching stop, the third insulating layer is removed by isotropic etching. A dielectric layer is formed on exposed surfaces of the storage electrode. A second conductive layer, which acts as an opposed electrode of the capacitor, is formed on the dielectric layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates in general to a method of fabricatingsemiconductor memory devices, and more particularly to a method offorming a capacitor with a storage electrode constructed with a verticalframe and a horizontal plate, wherein the horizontal plate has aplurality of extensions extending out vertically.

2. Description of Related Art

A DRAM (dynamic random access memory) is a widely used integratedcircuit device, and plays an indispensable role in the electronicindustry. FIG. 1 is a circuit diagram illustrating a conventional DRAMmemory cell. As shown in FIG. 1, a memory cell includes a transfertransistor T and a storage capacitor C. The source electrode of thetransfer transistor T is coupled to a corresponding bit line BL, thedrain electrode of the transfer transistor T is coupled to a storageelectrode 6 of the storage capacitor C, and the gate electrode of thetransfer transistor T is coupled to a corresponding word line WL. Anopposed electrode 8 of the storage capacitor C is coupled to astationary voltage source VCP. A dielectric layer 7 is deposited betweenthe storage electrode 6 and the opposed electrode 8. As known by thoseskilled in this art, the storage capacitor C is used for storing data,and should have enough capacitance to avoid a loss of data.

In a conventional fabricating process for a DRAM device having a storagecapacity below 1 MB, a two dimensional capacitance device, e.g., aplanar-type capacitor, is widely used for storing data. As shown in FIG.2, a field oxide layer 11 is formed on a substrate 10 to define anactive region, then gate oxide layer 12, gate electrode layer 13, andsource and drain electrode areas 14 are formed in sequence to form atransfer transistor T. On the surface of the substrate 10, a dielectriclayer 7 and a conductive layer 8 are formed on one side adjacent to thedrain. The area where the dielectric layer 7 and the conductive layer 8join with the substrate 10 forms a storage capacitor C. However, theplanar-type capacitor occupies a relatively large surface area of thedevice to form the storage capacitor C, which is at odds with the desirefor large scale integration of the DRAM device.

A highly integrated DRAM, e.g., with a storage capacity of 4 MB orabove, needs to use a three dimensional capacitance structure, such as astack-type capacitor or a trench type capacitor, in order to realize astructure with reduced surface area requirements.

FIG. 3 is a cross-sectional diagram illustrating the structure of aconventional stack-type capacitor. On a substrate 10, a field oxidelayer 11, a gate oxide layer 12, a gate electrode layer 13, and sourceand drain electrode areas 14 are formed in sequence to construct atransfer transistor T. Next, an insulating layer 15 is formed and acontact opening is formed by etching the source-drain electrode areas14. Thereafter, a first polysilicon layer 6, which is used as a storageelectrode, a dielectric layer 7 and a second polysilicon layer 8, whichis used as an opposed electrode, are formed in sequence on the device.In this way, a DRAM memory cell with stack-type capacitor C iscompleted. A memory cell should offer enough capacitance to assure theoperational quality of the device as the size of the device isdiminished. However, when a memory cell is even more highly integrated,such as when fabricating a DRAM with a storage capacity of 64 MB orabove, the above mentioned structure of a stack-type capacitor is nolonger adequate.

FIG. 4 is a cross-sectional diagram illustrating a structure ofconventional trench-type capacitor C. First, a transfer transistor T isformed on a substrate 10 by ordinary processing, including a gate oxidelayer 12, a gate electrode layer 13, and source and drain electrodeareas 14. On the surface of the substrate 10, a deep trench is etched onthe side adjacent to the drain electrode 14. Next, a storage capacitor Cis formed within the deep trench. The storage capacitor C includes adielectric layer 7, an opposed electrode polysilicon layer 8 and astorage electrode 6 which is formed by the sidewalls of the substrate10. However, to raise the capacitance, the structure and the fabricatingmethod of this kind of capacitor may increase the surface area ofelectrode. Further, during the forming of the deep trench by etching,lattice defects will be generated on the substrate that increase currentleakage and influence the characteristics of devices. Also, as theaspect ratio is increased, the etching rate will be decreased which addsto the difficulty of processing and adversely affects the efficiency ofproduction.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a methodof fabricating DRAM memory cells which maintains the requiredcapacitance for high levels of integration while the horizontaldimensions of the storage capacitor are decreased.

It is therefore another object of the present invention to provide amethod of fabricating a DRAM memory cell to form a capacitor structurewith a storage electrode having a vertical frame and a horizontal plate,wherein the horizontal plate has a plurality of extending areasextending out vertically on upper and lower surfaces thereof to increasethe surface area of the storage electrode and raise its capacitance.

According to a first aspect of the present invention, a method offabricating a DRAM memory cell which achieves the above-identifiedobjects includes the following steps. A transfer transistor having agate electrode and source-drain electrode areas is formed on asemiconductor substrate. First, second and third insulating layers areformed in sequence on the semiconductor substrate and the transfertransistor. The first, second and third insulating layers (in reverseorder) are selectively etched through down to the surface of thetransfer transistor to form a contact opening exposing one of thesource-drain electrode areas as a contact area. The upper portion of thethird insulating layer is etched to form a plurality of first trenches.A first conductive layer is formed over the insulating layers fillingthe contact opening and the plurality of first trenches. An upperportion of the first conductive layer is etched to form a plurality ofsecond trenches. The first conductive layer is thereby defined to have avertical frame and a horizontal plate. The vertical frame extends to thecontact area through the contact opening. The horizontal plate has aplurality of extending areas extending out vertically from its upper andlower surfaces by virtue of the first and second trenches. A patternarea of the storage electrode of a capacitor is defined by selectivelyetching the first conductive layer. Using the second insulating layer asan etching stop, the third insulating layer is removed by isotropicetching. A dielectric layer is formed on the exposed surface of thestorage electrode. A second conductive layer, which acts as an opposedelectrode of the capacitor, is formed on the dielectric layer, thuscompleting the DRAM memory cell fabrication process according to thisaspect of the invention.

According to a second aspect of the present invention, a method offabricating a DRAM memory cell which achieves the above-identifiedobjects, includes the following steps. A transfer transistor having agate electrode and source-drain electrode areas is formed on asemiconductor substrate. First, second and third insulating layers areformed in sequence on the semiconductor substrate and the transfertransistor. The third, second, and first insulating layers are, in thisorder, etched through down to the surface of the substrate to form acontact opening exposing one of the source-drain electrode areas as acontact area. A columnar conductive layer is formed filling the contactopening. An upper portion of the third insulating layer is etched toform a plurality of first trenches. A first conductive layer is formedextending over the third insulating layer and filling the firsttrenches. An upper portion of the first conductive layer is etched toform a plurality of second trenches, so that both upper and lowersurfaces of the first conductive layer then have a plurality ofextending areas extending out vertically therefrom. The pattern of thefirst conductive layer is defined by selectively etching the firstconductive layer, forming the storage electrode of a capacitor whichincludes the columnar conductive layer and the first conductive layerhaving the plurality of extending areas. Using the second insulatinglayer as an etching stop, the third insulating layer is removed byisotropic etching. A dielectric layer is formed on the exposed surfacesof the storage electrode. A second conductive layer, which acts as anopposed electrode of the capacitor, is formed on the dielectric layer,thus completing the DRAM memory cell fabrication process according tothis aspect of the invention.

According to a third aspect of the present invention, a method offabricating a DRAM memory cell which achieves the above-identifiedobjects, includes the following steps. A transfer transistor having agate electrode and source-drain electrode areas is formed on asemiconductor substrate. First and second insulating layers are formedin sequence on the semiconductor substrate and the transfer transistor.The second and first insulating layers are, selectively etched throughdown to the surface of the semiconductor substrate to form a firstcontact opening exposing one of the source-drain electrode areas as acontact area. A first conductive layer is formed extending over thesecond insulating layer and filling the first contact opening. A thirdinsulating layer is formed on the first conductive layer. A secondcontact opening is formed in the third insulating layer down the firstconductive layer. An upper portion of the third insulating layer is alsoetched to form a plurality of first trenches. A second conductive layeris formed extending over the third insulating layer, and filling thesecond contact opening and the plurality of the first trenches. An upperportion of the second conductive layer is etched to form a plurality ofsecond trenches. The structure of the second conductive layer is thusdefined to have a vertical frame coupled to the contact area through thefirst and second contact openings, and a horizontal plate with aplurality of extending areas. Using the second insulating layer as anetching stop, the second conductive layer, the third insulating layerand the first conductive layer are etched in sequence to define thepattern of the second conductive layer. The storage electrode of acapacitor thus includes the second and the first conductive layers. Thethird insulating layer is removed by isotropic etching, and a dielectriclayer is formed on the exposed surface of the storage electrode. A thirdconductive layer, which acts as an opposed electrode of the capacitor,is formed on the dielectric layer, thus completing the memory cellfabrication process according to the invention.

According to a fourth aspect of the present invention, a method offabricating a DRAM memory cell which achieves the above-identifiedobjects includes the following steps. A transfer transistor having agate electrode and source-drain electrode areas is formed on asemiconductor substrate. First, second and third insulating layers areformed in sequence on the semiconductor substrate and the transfertransistor. The third, second and first insulating layers areselectively etched through down to the surface of the semiconductorsubstrate to form a contact opening exposing one of the source-drainelectrode areas as a contact area. A first conductive layer is formedextending over the surface of the third insulating layer and filling thecontact opening. A fourth insulating layer is formed over the firstconductive layer, and a second contact opening is formed in the fourthinsulating layer down to the surface of the first conductive layer. Anupper portion of the fourth insulating layer is etched to form aplurality of first trenches. A second conductive layer is formedextending over the fourth insulating layer, and filling the secondcontact opening and the plurality of first trenches. An upper portion ofthe second conductive layer is etched to form a plurality of secondtrenches, and the structure of the second conductive layer is thusdefined to have a vertical frame and a horizontal plate. The verticalframe is coupled to the contact area through the first and secondcontact openings. The horizontal plate has a plurality of extendingareas extending out vertically on its upper and lower surfaces. Usingthe second insulating layer as an etching stop, the second conductivelayer, the fourth insulating layer, the first conductive layer and thethird insulating layer are etched in sequence to define a pattern areaof a storage electrode of a capacitor, which includes the second andfirst conductive layers. The fourth and the third insulating layers areremoved by isotropic etching, and a dielectric layer is formed on theexposed surface of the storage electrode. A third conductive layer,which acts as an opposed electrode of the capacitor, is formed on thedielectric layer, thus completing the memory cell fabrication processaccording to this aspect of the invention.

The extending areas extending out vertically from the horizontal platemay be disposed symmetrically or asymmetrically on the upper and/orlower surfaces of the horizontal plates.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features, and advantages of the present invention willbecome apparent by way of the following detailed description of thepreferred but non-limiting embodiments. The description is made withreference to the accompanying drawings in which:

FIG. 1 is a circuit diagram illustrating a conventional DRAM memorycell;

FIG. 2 is a cross-sectional diagram illustrating the structure of aconventional DRAM memory cell with a planar-type capacitor;

FIG. 3 is a cross-sectional diagram illustrating the structure of aconventional DRAM memory cell with a stack-type capacitor;

FIG. 4 is a cross-sectional diagram illustrating the structure of aconventional memory cell with a trench-type capacitor;

FIGS. 5A to 5F are cross-sectional diagrams illustrating the memory cellfabrication process of a first preferred embodiment according to thepresent invention;

FIGS. 6A to 6D are cross-sectional diagrams illustrating the memory cellfabrication process of a second preferred embodiment according to thepresent invention;

FIGS. 7A to 7B are cross-sectional diagrams illustrating the memory cellfabrication process of a third preferred embodiment according to thepresent invention;

FIGS. 8A to 8F are cross-sectional diagrams illustrating the memory cellfabrication process of a fourth preferred embodiment according to thepresent invention;

FIGS. 9A to 9D are cross-sectional diagrams illustrating the memory cellfabrication process of a fifth preferred embodiment according to thepresent invention;

FIGS. 10A to 10F are cross-sectional diagrams illustrating the memorycell fabrication process of a sixth preferred embodiment according tothe present invention; and

FIGS. 11A to 11D are cross-sectional diagrams illustrating the memorycell fabrication process of a seventh preferred embodiment according tothe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiment 1

As shown in FIG. 2, conventionally a field oxide layer 11 is formed on asilicon substrate 10 to define the area of an active region. Next, gateoxide layer 12, polysilicon gate electrode layer 13 and dopedsource-drainareas 14 are formed in sequence to construct the transfertransistor T. Up to this point in the process, the method according tothe invention is same as the conventional process of FIG. 2. Forconvenience and simplification in illustrating the invention, the abovementioned structure of the transfer transistor, etc., will beillustrated only as a flat substrate 20 in FIGS. 5A to 5E.

Referring FIG. 5A, a first insulating layer 25, a second insulatinglayer 26 and a third insulating layer 27 are formed in sequence on thesubstrate20. For example, first, a borophosphosilicate glass firstinsulating layer 25 is formed to a thickness of about 7000Å as apassivation layer by chemical vapor deposition (CVD). Next, a siliconnitride second insulatinglayer 26 is deposited with a thickness of about1000Å as a etching protecting layer by CVD. Then, after depositing asilicon oxide third insulating layer 27 with a thickness of about 7000Å,the third, second, and first insulating layers 27, 26 and 25 areselectively etched through down to the surface of the substrate 20 toform a contact opening 28 exposing one of the source-drain electrodeareas (not shown in FIG. 5, but refer to 14 in FIG. 2 for example) as acontact area.

Referring to FIG. 5B, using photolithography and etching, a plurality offirst trenches 29 are formed on an upper portion of the third insulatinglayer 27. For example, the upper portion of the above mentioned siliconoxide layer 27 is etched by reactive ion etching (RIE) to apredetermined depth. The shape of the first trenches 29 could berectangular, cylindrical or polygonal, for example, and the number oftrenches may be adjusted as needed.

As shown in FIG. 5C, a first conductive layer 30 is formed over thethird insulating layer 27 filling the contact opening and the pluralityof first. trenches 29. For example, a polysilicon first conducting layer30 is deposited with a thickness of about 7000Å by CVD. Thereafter, aplurality of second trenches 31 are formed on an upper portion of thefirst conductive layer 30. The shape of the second trenches 31 could berectangular, cylindrical or polygonal, for example. Also, in theillustrated exemplary embodiment, the second trenches and the firsttrenches are disposed to be complementary to each other.

As illustrated in FIG. 5D, using photoresist mask (not shown), the firstconductive layer 30 is etched by anisotropic etching, e.g., reactive ionetching, to define a pattern area of the capacitor. After thephotoresist is removed, using the second insulating layer 26 (siliconnitride) as an etching stop, the third insulating layer 27 (siliconoxide layer) is removed by isotropic etching, e.g., wet etching using,for example, HF (hydrofluoric acid) or B.O.E.(buffered oxide etchant).Up to this point inthe process, the structure of the first conductivelayer 30 defines the storage electrode 60 of a capacitor including avertical frame 41 and a horizontal plate 42. The vertical frame 41 iscoupled to the contact area of the substrate 20 through the contactopening 28. The horizontal plate 42 has a plurality of extending areas43a and 43b which bulge out (extend)vertically and are disposedsymmetrically on its upper and lower surfaces as shown.

As shown in FIG. 5E, a dielectric layer 70 is formed on the storageelectrode 60. The dielectric layer 70 could be a two layer structure,e.g., silicon nitride/silicon dioxide (NO) layers, or a three layerstructure, e.g., silicon dioxide/silicon nitride/silicon dioxide (ONO)layers or other materials could be used, such as tantalum oxide, bariumtitanic acid, or strontium titanic acid. On the surface of thedielectric layer 70, an opposed electrode 80 is formed, thus completingthe fabrication of the capacitor of a DRAM memory cell. For example,opposed electrode 80 could be a polysilicon layer deposited to athickness of about 1000Å by CVD. The polysilicon layer 80 could also beimplanted with impurities to increase conductivity. Then, a pattern areaof the polysilicon layer 80 is defined by photolithography and etchingto form the opposed electrode of the capacitor C. The above mentionedstorage electrode 60, the dielectric layer 70 and the opposed electrode80 together form capacitor C.

For convenience and simplification of description and illustration, thesemiconductor substrate 20 is shown flat in the figures. That is, anyroughness of the surface caused by the field oxide layer 11 and thepolysilicon gate layer 13 is not shown in the previous figures. Whenconsidering the surface roughness, the structure of the DRAM memory cellaccording to the present invention will be the structure illustrated inFIG. 5F. It is clear that in either FIGS. 5E or 5F, the horizontal plate42 of the storage electrode 60 has a plurality of extending areas on itsupper and lower surfaces that increase the surface area of the storageelectrode 60 to provide more capacitance within the same horizontaldimensions. By controlling the quantity of extending areas 43a and 43bto thereby adjust the surface area of the storage electrode 60, therequired capacitance is achieved.

Embodiment 2

First, performing the process steps as shown in FIGS. 5A to 5B andalready described, a first insulating layer 25, a second insulatinglayer 26 and athird insulating layer 27 are formed in sequence on asubstrate 20, and etched to form a contact opening 28 and a plurality offirst trenches 29. Next, referring to FIG. 6A, a first conductive layer30 is formed over thethird insulating layer 27 filling the contactopening 28 and the first trenches 29. For example, a polysiliconconducting layer 30 is deposited to a thickness of about 7000Å by CVD.Thereafter, using photolithography and etching, a plurality of secondtrenches 31 are formedon an upper portion of the first conductive layer30. The shape of the second trenches 31 could be rectangular,cylindrical or polygonal, for example, and the number of second trenchescould be adjusted as needed.

Performing the process shown in FIG. 5D of embodiment 1, a pattern areaof the first conductive layer 30 is defined by anisotropic etching toconstruct the storage electrode 60 of a capacitor. The third insulatinglayer 27 is removed by isotropic etching to obtain a structure with avertical frame 41 and a horizontal plate 42, as shown in FIG. 6B. Thevertical frame 41 is coupled to the contact area of the substrate 20through the contact opening 28. The horizontal plate 42 has a pluralityofextending areas 43a and 43b which extend out vertically and aredisposed asymmetrically on the upper and lower surfaces of thehorizontal plate 42.

As shown in FIG. 6C, a dielectric layer 70 is formed on the storageelectrode 60. The dielectric layer 70 could be a two layer structure,e.g., silicon nitride/silicon dioxide (NO) layers, or a three layerstructure, e.g., silicon dioxide/silicon nitride/silicon dioxide (ONO)layers or other materials, such as tantalum oxide, barium titanic acid,orstrontium titanic acid. Thereafter, a polysilicon layer is depositedto a thickness of about 1000Å by CVD. The polysilicon layer could beimplanted with impurities to increase conductivity. Then, a pattern areaof the polysilicon layer is defined by photolithography and etching toform opposed electrode 80 of the capacitor. The storage electrode 60,the dielectric layer 70 and the opposed electrode 80 together form acapacitorC, thus completing the process of fabricating a DRAM memorycell.

For the convenience of description and illustration, the semiconductorsubstrate 20 is shown flat in FIGS. 6A to 6C. However, consideringsurfaceroughness, the structure of the DRAM memory cell according to thepresent invention would be the structure as shown in FIG. 6D. It isclear that in FIGS. 6C or 6D, the horizontal plate 42 of the storageelectrode 60 has a plurality of extending areas on the upper and lowersurfaces that could increase the surface area of the storage electrode60 to provide more capacitance within the same horizontal dimensions.

Embodiment 3

In the first and second exemplary embodiments, since the firstconductive layer 30 is deposited to fill the contact opening 28 and thefirst trenches 29 at the same time, as the depth difference between thecontact opening 28 and the first trenches 29 increases, it becomesdifficult to obtain a planar surface. Thus, the third exemplaryembodiment is provided as another solution to the stated problem.

Referring to FIG. 7A, a substrate 20 is provided having a field oxidelayer, a gate oxide layer, a gate polysilicon layer and source-drainelectrode areas, which are not shown for simplification of illustrationand explanation. A first insulating layer 25, a second insulating layer26, and a third insulating layer 27, e.g., a borophosphosilicate glasslayer 25, a silicon nitride layer 26 and a silicon oxide layer 27, areformed on substrate 20 in sequence. A contact opening 28 is formed byphotolithography and etching exposing one of the source-drain electrodeareas as a contact area. Thereafter, a columnar conductive layer 35,e.g.,a polysilicon layer, is formed to fill the contact opening 28 byCVD.

In FIG. 7B, using photolithography and etching, a plurality of a firsttrenches 29 are formed on an upper portion of the third insulating layer27. Thereafter, performing the processing as shown in FIGS. 5C to 5E, orthe processing as shown in FIGS. 6A to 6C, a DRAM structure, as shown inFIGS. 5F or 6D, will be obtained. The structure formation according tothis embodiment is easier to perform because the first conductive layerishere only formed to fill the first trenches 29 and not to also fillthe contact opening. The storage electrode 60 is constructed by thecolumnar conductive layer 35 and the first dielectric layer 30. Thecapacitance is raised due to the horizontal plate having a plurality ofextending areas on its upper and lower surfaces.

Embodiment 4

As shown in FIG. 2, conventionally a field oxide layer 11 is formed on asilicon substrate 10 to define the area of an active region. Next, agate oxide layer 12, a gate polysilicon layer 13 and doped source-drainareas 14 are formed in sequence to construct a transfer transistor T. Upto thispoint, the method according to the invention is same as theconventional process of FIG. 2. For convenience of description andsimplification in illustrating the invention, the above mentionedstructure of the transfer transistor, etc., will be shown only as a flatsubstrate 20 in FIGS. 8A to8E.

Referring to FIG. 8A, a first insulating layer 25 and a secondinsulating layer 26 are deposited in sequence on the substrate 20. Forexample, first, a borophosphosilicate glass first insulating layer 25 isdeposited to a thickness of about 7000Å as a passivation layer bychemical vapordeposition (CVD). Next, a silicon nitride secondinsulating layer 26 is deposited by CVD to a thickness of about 1000Å asa etching protectinglayer. The second and first insulating layers 26, 25are selectively etchedthrough down to the surface of the substrate 20 toform a first contact opening 50 exposing one of the source-drainelectrode areas (not shown) asa contact area. Then, a first conductivelayer 52, e.g., a polysilicon layer, is formed over the secondinsulating layer 26 to a thickness of about 5000Å by CVD filling thefirst contact opening 50. The polysilicon layer 52 contacts the contactarea of the substrate through the first contact opening 50.

Referring next to FIG. 8B, a third insulating layer 27 is formed overthe first conductive layer 52. For example, a silicon oxide thirdinsulating layer 27 is deposited to a thickness of about 7000Å by CVD.Using photolithography and etching, a second contact opening 28 isformed on thethird insulating layer 27 directly above the first contactopening 50 exposing the surface of the conductive layer 52, and aplurality of first trenches 29 are formed on an upper portion of thethird insulating layer 27. The shape of the first trenches 29 could berectangular, cylindrical or polygonal, for example, and the number offirst trenches 29 can be adjusted as needed.

As shown in FIG. 8C, a second conductive layer 30 is formed over thethird insulating layer 27 filling the second contact opening 28 and theplurality of first trenches 29. For example, a polysilicon secondconductive layer 30 is deposited to a thickness of about 7000Å by CVDand coupled to the first conductive layer 52 through the second contactopening 28. Thereafter, a plurality of second trenches 31 are formed onanupper portion of the second conductive layer 30. The shape of thesecond trenches 31 could be rectangular, cylindrical or polygonal, andtheir number can be adjusted as needed. As illustrated, in thisexemplary embodiment, the second trenches and the first trenches aredisposed to be complementary to each other.

As illustrated in FIG. 8D, using a photoresist mask (not shown), thesecondconductive layer 30, the third insulating layer 27 and the firstconductivelayer 52 are etched by anisotropic etching, e.g., reactive ionetching, to define a pattern area of the capacitor. After thephotoresist is removed, using the second insulating layer 26 (siliconnitride) as an etching stop,the third insulating layer 27 (silicon oxidelayer) is removed by isotropicetching, e.g., wet etching using forexample, HF (hydrofluoric acid) or B.O.E.(buffered oxide etchant). Up tothis point in the process, the structure of the first and secondconductive layers 52, 30 defines the storage electrode 60 of acapacitor, which includes a vertical frame 41, afirst horizontal plate55 and a second horizontal plate 42. The vertical frame 41 contacts thecontact area of the substrate 20 through the contactopenings 28 and 50.The first and second horizontal plates 55, 42 are formed apart insequence and extend parallel with the surface of the second insulatinglayer 26. The second horizontal plate 42 has a pluralityof extendingareas 43a and 43b extending out vertically and formed symmetrically onthe upper and lower surfaces of the horizontal plate 42 as shown.

As illustrated in FIG. 8E, a dielectric layer 70 is formed over theexposedsurface of the storage electrode 60. The dielectric layer 70could be a twolayer structure, e.g., silicon nitride/silicon dioxide(NO) layers, or a three layer structure, e.g., silicon dioxide/siliconnitride/silicon dioxide (ONO) layers or other materials could be usedsuch as tantalum oxide, barium titanic acid, or strontium titanic acid.On the surface of the dielectric layer 70, an opposed electrode 80 isformed, thus completing the fabrication of the capacitor of a DRAMmemory cell. For example, a polysilicon layer is deposited to athickness of about 1000Å by CVD. The polysilicon layer could beimplanted with impuritiesto increase conductivity. Then, a pattern areaof the polysilicon layer is defined by photolithography and etching toform opposed electrode 80 of the capacitor. Thus, the storage electrode60, the dielectric layer 70 andthe opposed electrode 80 together formcapacitor C.

When considering the roughness caused by field oxide layer 11 andpolysilicon gate layer 13, for example, the structure of the DRAM memorycell according to the present invention will be the structure as shownin FIG. 8F. It is clear that in either FIGS. 8E or 8F, the secondhorizontal plate 42 of the storage electrode 60 formed with a pluralityof extending areas on both the upper and lower surfaces, increases thesurface area of the storage electrode 60. Since the first horizontalplate 55 provides an additional surface, the capacitance of thisembodiment is significantly higher than the capacitance of embodiments1, 2 and 3 for example.

Embodiment 5

This exemplary embodiment is based on the structure and fabricationprocessof FIGS. 8A and 8B of exemplary embodiment 4. Referring to FIG.9A, a second conductive layer 30 is formed over the third insulatinglayer 27 filling the second contact opening 28 and the plurality offirst trenches 29. For example, a polysilicon second conductive layer 30is deposited to a thickness of about 7000Å by CVD, and coupled to thefirst conductivelayer 52 through the second contact opening 28. Then,using photolithography and etching, a plurality of second trenches 31are formedon an upper portion of the second conductive layer 30 in adifferent orientation from the previous embodiment.

Next, performing the process as shown in FIG. 8D, using anisotropicetching, a pattern area is defined by etching the second conductivelayer 30, the third insulating layer 27 and the first conductive layer52. Then the second insulating layer 26 is removed by isotropic etchingto obtain the storage electrode 60 of a capacitor as shown in FIG. 9B.The storage electrode 60 includes a vertical frame 41, a firsthorizontal plate 55 anda second horizontal plate 42. The vertical frame41 is coupled to the contact area of the substrate 20 through thecontact openings 28 and 50. The second horizontal plate 42 has aplurality of extending areas 43a and 43b extending out vertically fromupper and lower surfaces of the horizontal plate 42, but in a differentshape than in the fourth embodiment.

As shown in FIG. 9C, a dielectric layer 70 is formed over the exposedsurface of the storage electrode 60. An opposed electrode 80 is formedon the surface of the dielectric layer 70. Thus, the storage electrode60, the dielectric layer 70 and the opposed electrode 80 together form acapacitor C. The steps and the exemplary materials used in this processare the same as in the above previously mentioned embodiments.

When considering the roughness caused by field oxide layer 11 andpolysilicon gate layer 13, for example, the structure of the DRAM memorycell according to the present invention will be the structure as shownin FIG. 9F. It is clear that in FIG. 8F, the surface area of the storageelectrode 60 is significantly increased which efficiently raises thecapacitance.

Embodiment 6

This exemplary embodiment is based on the process and structure ofexemplary embodiment 4 previously described. With reference to FIG. 10A,afirst insulating layer 25, a second insulating layer 26 and a thirdinsulating layer 51 are formed in sequence on the substrate 20. Forexample, a borophosphosilicate glass first insulating layer 25, asilicon nitride second insulating layer 26 and a silicon oxide thirdinsulating layer 51 are formed by CVD. The third, second and firstinsulating layers 51, 26, 25 (in that order) are selectively etchedthrough down to the surface of the substrate 20 to form a first contactopening 50 for exposing one of the source-drain electrode areas (notshown) as a contact area. Then, a first conductive layer 52, e.g., apolysilicon layer, is formed over the third insulating layer 51 to athickness of about 5000Å by CVD also filling the first contact opening50, and making contact with the contact area on the substrate 20 throughthe first contact opening 50.

Referring to FIG. 10B, a fourth insulating layer 27 is formed over thefirst conductive layer 52. For example, a silicon oxide fourthinsulating layer 27 is deposited to a thickness of about 7000Å by CVD.Using photolithography and etching, a second contact opening 28 isformed on thefourth insulating layer 27 directly above the first contactopening 50 exposing the surface of the first conductive layer 52, and aplurality of first trenches 29 are formed on an upper portion of thefourth insulating layer 27. The shape of the first trenches 29 may berectangular, cylindrical or polygonal, and their number may be adjustedas needed.

As shown in FIG. 10C, a second conductive layer 30 is formed over thefourth insulating layer 27 filling the second contact opening 28 and theplurality of first trenches 29. For example, a polysilicon layer 30 isdeposited to a thickness of about 7000Å by CVD making contact withthefirst conductive layer 52 through the second contact opening 28.Thereafter, using photolithography and etching, a plurality of secondtrenches 31 are formed on an upper portion of the second conductivelayer 30. The shape of the second trenches 31 may be rectangular,cylindrical orpolygonal, and their number may be adjusted as needed.Also, as shown in the exemplary embodiment, the second trenches 31 andthe first trenches 29are disposed to be complementary to each other.

As illustrated in FIG. 10D, using a photoresist mask (not shown), thesecond conductive layer 30, the fourth insulating layer 27 and the firstconductive layer 52 are etched by anisotropic etching, e.g., reactiveion etching to define a pattern area of a capacitor. After thephotoresist is removed, using the second insulating layer 26 (siliconnitride layer) as an etching stop, the third insulating layer 51(silicon oxide layer) is removed by isotropic etching. Up to this pointin the process, the structure of the first and second conductive layers52, 30 defines the storage electrode 60 of a capacitor, which includes avertical frame 41, afirst horizontal plate 55 and a second horizontalplate 42. The vertical frame 41 contacts the contact area of thesubstrate 20 through the first and second contact openings 28 and 50.The first and second horizontal plates 55, 42 are formed apart insequence and extend parallel with the surface of the second insulatinglayer 26. The second horizontal plate 42 has a plurality of extendingareas 43a and 43b which extend out verticallyand are disposedsymmetrically on the upper and lower surfaces of the horizontal plate42, as shown.

As illustrated in FIG. 10E, a dielectric layer 70 is formed over theexposed surface of the storage electrode 60. On the surface of thedielectric layer 70, an opposed electrode 80 is formed, thus completingthe fabrication of the capacitor of a DRAM memory cell. The steps andthe exemplary materials used in this part of the process are the same asin the above previously described exemplary embodiments, and thereforewill not be described again.

When considering the roughness caused by field oxide layer 11 andpolysilicon gate layer 13, for example, the structure of the DRAM memorycell according to the present invention will be the structure as shownin FIG. 10F. It is clear that, in either FIGS. 10E or 10F, the surfacearea of the storage electrode 60 is significantly increased by virtue ofthe spacing (gap 45) between the first horizontal plate 55 and thesecond insulating layer 26 that efficiently increases the capacitancepossible.

Embodiment 7

This exemplary embodiment is based on the structure and process ofexemplary embodiment 6 shown in FIGS. 10A to 10B and will be describedusing the same reference numerals. As shown in FIG. 11A, a secondconductive layer 30 is formed over the fourth insulating layer 27filling the second contact opening 28 and the plurality of the firsttrenches 29. For example, a polysilicon layer 30 is deposited to athickness of about 7000Å by CVD and contacts the first conductive layer52 through the second contact opening 28. Thereafter, usingphotolithography and etching,a plurality of second trenches 31 areformed on the upper portion of the second conductive layer 30 asillustrated.

Next, performing the same process as shown in FIG. 10D, the secondconductive layer 30, the fourth insulating layer 27, the firstconductive layer 52 and the third insulating layer 51 are etched byanisotropic etching to define a pattern area of a capacitor. Then, thefourth and third insulating layers 27, 51 are removed by isotropicetching to obtain the structure as shown in FIG. 11B, forming thestorage electrode 60 of a capacitor having the first and secondconductive layers 52, 30. The storage electrode 60 includes a verticalframe 41, a first horizontal plate 55 and a second horizontal plate 42.The vertical frame 41 is coupled to the contact area of the substrate 20through the first and second contact openings 50 and 28. The first andsecond horizontal plates 55, 42 are formed apart in sequence and extendparallel with the surface of the second insulating layer 26. A gap 45 isthus formed between the first horizontal plate 42 and the secondinsulating layer 26. The second horizontal plate 42 has a plurality ofextending areas 43a and 43b which extend out vertically and are disposedasymmetrically on the upper and lower surfaces of the horizontal plate42.

As shown in FIG. 11C, a dielectric layer 70 is formed over the exposedsurface of the storage electrode 60. On the surface of the dielectriclayer 70, an opposed electrode 80 is formed, thus completing thefabrication of the capacitor of a DRAM memory cell. The steps and thematerials used in this process are the same as in the above previouslymentioned and illustrated exemplary embodiments, and therefore will notbedescribed again.

When considering the roughness caused by field oxide layer 11 andpolysilicon gate layer 13, for example, the structure of the DRAM memorycell according to the present invention will be the structure as shownin FIG. 11D. It is clear that, in FIGS. 11C or 11D, the surface of thestorage electrode 60 is significantly increased not only by thestructure of the second horizontal plate 42 of the storage electrode 60,but also byvirtue of the gap 45 separating the first horizontal plate 55from the second insulating layer 26 that efficiently increases thecapacitance possible.

For those skilled in the art, it should be apparent that thecharacteristics of the previously described preferred embodiments may beused individually or simultaneously, to build a variety of differentkindsof storage electrodes. All sorts of variations in the structure ofthe storage electrodes are considered to be within the scope of thepresent invention as defined in the claims. It should be noted thatalthough the drain electrodes of the exemplary transfer transistorillustrated are in adiffusion area of the silicon substrate, the presentinvention is not limited to this particular transistor structure. Otherkinds of drain electrode structures could be used with the presentinvention, such as a trench type drain electrode structure, for example.

While the invention has been described by way of examples and in termsof preferred embodiments, it is to be understood that the invention isnot limited to the disclosed exemplary embodiments. To the contrary, thescopeof the invention is intended to include various modifications andsimilar arrangements within the spirit of the invention limited only bythe appended claims, which should be accorded the broadestinterpretation so as to encompass all such modifications and similarstructures.

What is claimed is:
 1. A method of fabricating a DRAM cell, comprisingthe steps of:(a) forming a transfer transistor having a gate electrodeand source-drain electrode areas on a semiconductor substrate; (b)forming first, second and third insulating layers in sequence on thesemiconductor substrate and the transfer transistor; (c) forming acontact opening by seriatim etching through the third, second and firstinsulating layers exposing one of the source-drain electrode areas ofthe transfer transistor as a contact area; (d) forming a plurality offirst trenches by etching an upper portion of the third insulating layer(e) forming a first conductive layer extending over the third insulatinglayer and filling the contact opening and the plurality of firsttrenches; (f) forming a plurality of second trenches by etching an upperportion of the first conductive layer, wherein the structure of thefirst conductive layer thereby includes a vertical frame contacting thecontact area through the contact opening, and a horizontal plate havinga plurality of extending areas which extend out vertically therefrom onupper and lower surfaces thereof; (g) selectively etching the firstconductive layer to define a pattern of a storage electrode of acapacitor; (h) using the second insulating layer as an etching stop,removing the third insulating layer by isotropic etching; (i) forming adielectric layer on exposed surfaces of the storage electrode; and (j)forming a second conductive layer, which acts as an opposed electrode ofthe capacitor, on the dielectric layer.
 2. The method of fabricating aDRAM cell according to claim 1, wherein the first insulating layercomprises a borophosphosilicate glass layer, the second insulating layercomprises a silicon nitride layer, and the third insulating layercomprises a silicon oxide layer.
 3. The method of fabricating a DRAMcell according to claim 1, wherein the plurality of second trenches areformed in step (f) so that the plurality of extending areas which extendout vertically are disposed symmetrically on the upper and lowersurfaces of the horizontal plate.
 4. The method of fabricating a DRAMcell according to claim 1, wherein the plurality of second trenches areformed in step (f) so that the plurality of extending areas which extendout vertically are disposed asymmetrically on the upper and lowersurfaces of the horizontal plate.
 5. The method of fabricating a DRAMcell according to claim 1, wherein the first conductive layer and thesecond conductive layer comprise polysilicon layers.
 6. A method offabricating a DRAM cell, comprising the steps of:(a) forming a transfertransistor having a gate electrode and source-drain electrode areas on asemiconductor substrate; (b) seriatim forming first, second and thirdinsulating layers on the semiconductor substrate and the transfertransistor; (c) forming a contact opening by selectively etching throughthe third, second, and first insulating layers exposing one of thesource-drain electrode areas as a contact area; (d) forming a columnarconductive layer filling the contact opening; (e) forming a plurality offirst trenches by etching an upper portion of the third insulatinglayer; (f) forming a first conductive layer extending over the thirdinsulating layer filling the first trenches and contacting the columnarconductive layer; (g) forming a plurality of second trenches by etchingan upper portion of the first conductive layer, wherein both upper andlower surfaces of the first conductive layer thereby have a plurality ofextending areas which extend out vertically therefrom; (h) selectivelyetching the first conductive layer to a define a pattern of a storageelectrode of a capacitor which includes the columnar conductive layerand the first conductive layer; (i) using the second insulating layer asan etching stop, removing the third insulating layer by isotropicetching; (j) forming a dielectric layer on exposed surfaces of thestorage electrode; and (k) forming a second conductive layer, which actsas an opposed electrode of the capacitor, on the dielectric layer. 7.The method of fabricating a DRAM cell according to claim 6, wherein thefirst insulating layer comprises a borophosphosilicate glass layer, thesecond insulating layer comprises a silicon nitride layer, and the thirdinsulating layer comprises a silicon oxide layer.
 8. The method offabricating a DRAM cell according to claim 6, wherein the plurality ofsecond trenches are formed in step (g) so that the plurality ofextending areas which extend out vertically are disposed symmetricallyon the upper and lower surfaces of the first conductive layer.
 9. Themethod of fabricating a DRAM cell according to claim 6, wherein theplurality of second trenches are formed by step (g) so that theplurality of extending areas which extend out vertically are disposedasymmetrically on the upper and lower surfaces of the first conductivelayer.
 10. The method of fabricating a DRAM cell according to claim 6,wherein the columnar conductive layer, the first conductive layer andthe second conductive layer are polysilicon layers.
 11. A method offabricating a DRAM cell, comprising the steps of:(a) forming a transfertransistor having a gate electrode and source-drain electrode areas on asemiconductor substrate; (b) seriatim forming first and secondinsulating layers on the semiconductor substrate and the transfertransistor; (c) forming a first contact opening by selectively etchingthrough the second insulating layer and the first insulating layersexposing one of the source-drain electrode areas as a contact area; (d)forming a first conductive layer extending over the second insulatinglayer, filling the first contact opening and contacting the contactarea; (e) forming a third insulating layer on the first conductive layerhaving a second contact opening disposed above the filled first contactopening exposing a portion of the surface of the first conductive layer;(f) forming a plurality of first trenches by etching an upper portion ofthe third insulating layer; (g) forming a second conductive layerextending over the third insulating layer, filling the second contactopening and the plurality of first trenches, and contacting the firstconductive layer; (h) forming a plurality of second trenches by etchingan upper portion of the second conductive layer, wherein the structureof the second conductive layer thereby includes a vertical framecontacting the first conductive layer through the second contactopening, and a horizontal plate having a plurality of extending areaswhich extend out vertically therefrom on upper and lower surfacesthereof; (i) using the second insulating layer as an etching stop,seriatim etching the second conductive layer, the third insulating layerand the first conductive layer to define a pattern of a storageelectrode of a capacitor which includes the second and first conductivelayers; (j) removing the third insulating layer by isotropic etching;(k) forming a dielectric layer on exposed surfaces of the storageelectrode; and (l) forming a third conductive layer, which acts as anopposed electrode of the capacitor, on the dielectric layer.
 12. Themethod of fabricating a DRAM cell according to claim 11, wherein thefirst insulating layer comprises a borophosphosilicate glass layer, thesecond insulating layer comprises a silicon nitride layer, and the thirdinsulating layer comprises a silicon oxide layer.
 13. The method offabricating a DRAM cell according to claim 11, wherein the plurality ofsecond trenches are formed in step (h) so that the plurality ofextending areas which extend out vertically are disposed symmetricallyon the upper and lower surfaces of the horizontal plate.
 14. The methodof fabricating a DRAM cell according to claim 11, wherein the pluralityof second trenches are formed by step (h) so that the plurality ofextending areas which extend out vertically are disposed asymmetricallyon the upper and lower surfaces of the horizontal plate.
 15. The methodof fabricating a DRAM cell according to claim 11, wherein, the first andsecond conductive layers comprise polysilicon layers.
 16. A method offabricating a DRAM cell, comprising the steps of:(a) forming a transfertransistor having a gate electrode and source-drain electrode areas on asemiconductor substrate; (b) seriatim forming first, second and thirdinsulating layers on the semiconductor substrate and the transfertransistor; (c) forming a first contact opening by selectively etchingthrough the third, the second and the first insulating layers exposingone of the source-drain electrode areas as a contact area; (d) forming afirst conductive layer extending over the third insulating layer andfilling the first contact opening; (e) forming a fourth insulating layerextending over the first conductive layer having a second contactopening disposed correspondingly above the first contact openingexposing a portion of the first conductive layer; (f) etching an upperportion of the fourth insulating layer forming a plurality of firsttrenches; (g) forming a second conductive layer extending over thefourth insulating layer, filling the second contact opening and theplurality of first trenches, and contacting the first conductive layer;(h) forming a plurality of second trenches by etching an upper portionof the second conductive layer, wherein the structure of the secondconductive layer thereby includes a vertical frame contacting the firstconductive layer through the second contact opening, and a horizontalplate having a plurality of extending areas which extend out verticallytherefrom on upper and lower surfaces thereof; (i) using the secondinsulating layer as an etching stop, seriatim etching the secondconductive layer, the fourth insulating layer, the first conductivelayer and the third insulating layer to define a pattern of a storageelectrode of a capacitor which includes the second and first conductivelayers; (j) removing the fourth and third insulating layers by isotropicetching; (k) forming a dielectric layer on exposed surfaces of thestorage electrode; and (l) forming a third conductive layer, which actsas an opposed electrode of the capacitor, on the dielectric layer. 17.The method of fabricating a DRAM cell according to claim 16, wherein thefirst insulating layer comprises a borophosphosilicate glass layer, thesecond insulating layer comprises a silicon nitride layer, and the thirdinsulating layer comprises a silicon oxide layer.
 18. The method offabricating a DRAM cell according to claim 16, wherein the plurality ofsecond trenches are formed in step (h) so that the plurality ofextending areas which extend out vertically are disposed symmetricallyon the upper and lower surfaces of the horizontal plate.
 19. The methodof fabricating a DRAM cell according to claim 16, wherein the pluralityof second trenches are formed by step (h) so that the plurality ofextending areas which extend out vertically are disposed asymmetricallyon the upper and lower surfaces of the horizontal plate.
 20. The methodof fabricating a DRAM cell according to claim 16, wherein the first,second and third conductive layers comprise polysilicon layers.